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integrated device technology, inc. commercial temperature ranges december 1996 1996 integrated device technology, inc. dsc-2753/8 5.37 1 idt72103 idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 features: 35ns parallel port access time, 45ns cycle time 50mhz serial input/output frequency serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel operations expandable in both depth and width with no external components flexishift ? ?sets programmable serial word width from 4 bits to any width with no external components multiple flags: full, almost-full (full-1/8),full-minus- one, empty, almost-empty (empty + 1/8), empty-plus one, and half-full asynchronous and simultaneous read or write operations dual-port, zero fall-through time architecture retransmit capability in single-device mode packaged in 44-pin plcc industrial temperature range (-40 o c to +85 o c) is avail- able, tested to military electrical specifications applications: high-speed data acquisition systems local area network (lan) buffer high-speed modem data buffer remote telemetry data buffer fax raster video data buffer laser printer engine data buffer high-speed parallel bus-to-bus communications magnetic media controllers serial link buffer description: the idt72103/72104 are high-speed parallel-serial flfos to be used with high-performance systems for functions such as serial communications, laser printer engine control and local area networks. a serial input, a serial output and two 9-bit parallel ports make four modes of data transfer possible: serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel. the idt72103/72104 are expandable in both depth and width for all of these operational configurations. functional block diagram the idt logo is a registered trademark of integrated device technology,inc. for latest information contact idt's web site at www.idt.com or fax-on-demand at 408-492-8391. 2753 drw 01 data inputs (d 0 -d ram array 2048 x 9 4096 x 9 write pointer read pointer flag logic ef aef hf ef+1 r 8 w depth expansion logic xi fl / rt serial output circuitry sox so ff-1 ff reset logic rs socp serial output data outputs (q 0 -q 8 ) xo oe serial/ parallel control so /po si /pi serial input circuitry six si sicp serial input )
5.37 2 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges description (continued) the idt72103/72104 may be configured to handle serial word widths of four or greater using idts unique flexishift feature. flexishift allows serial width and depth expansion without external components. for example, you may config- ure a 4k x 24 fifo using three idt72104s in a serial width expansion configuration. seven flags are provided to signal memory status of the fifo. the flags are ff (full), af (7/8 full), ffC1 (full-minus- one), ef (empty), ae (1/8 full), ef+1 (empty-plus-one), and hf (half-full). read ( r ) and write ( w ) control pins are provided for asynchronous and simultaneous operations. an output en- able ( oe ) control pin is available on the parallel output port for high-impedance control. the depth expansion control pins xo and xl are provided to allow cascading for deeper flfos. the idt72103/72104 are manufactured using idts cmos technology. pin configurations plcc top view 7 8 9 10 11 12 13 j44-1 39 38 37 36 35 34 33 432 1 43 index 5 64442 41 40 14 15 16 17 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d 0 xi so/po sox socp q 0 so aef ff-1 ff gnd fl/rt rs si sicp six gnd xo/hf ef ef+1 oe si/pi q 1 q 2 q 3 q 4 gnd r q 5 q 6 q 7 q 8 gnd v d 1 d 2 d 3 d 4 w cc d 5 d 6 d 7 d 8 gnd 2753 drw 03
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 3 capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 10 pf c out output capacitance v out = 0v 12 pf note: 2753 tbl 02 1. this parameter is sampled and not 100% tested. absolute maximum ratings (1) symbol rating commercial unit v term terminal voltage C0.5 to +7.0 v with respect to gnd t a operating temperature 0 to +70 c t bias temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c i out dc output current 50 ma 2753 tbl 01 note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions symbol parameter min. typ. max. unit v ccc commercial supply 4.5 5.0 5.5 v voltage gnd supply voltage 0 0 0 v v ih input high voltage 2.0 v commercial v il (1) input low voltage 0.8 v note: 2753 tbl 03 1. 1.5v undershoots are allowed for 10ns once per cycle. pin description symbol name i/o description d 0 -d 8 data inputs i/o in a parallel input configuration C data inputs for 9-bit wide data. serial input word in a serial input configuration C one of the nine output pins is used to select the serial input width select word width. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array. ef , ef+1 , aef are all low after a reset, while ff , ff-1 , hf are high after a reset. w write i a parallel word write cycle is initiated on the falling edge of w if the ff is high. when the fifo is full, ff will go low inhibiting further write operations to prevent data overflow. in a serial input configuration, data bits are clocked into the input shift register and the write pointer does not advance until a full parallel word is assembled. one of the pins, di, is connected to w and advances the write pointer every i-th serial input clock. r read i a read cycle is initiated on the falling edge of r if the ef is high. after all the data from the fifo has been read ef will go low inhibiting further read operations. in a serial output configuration, a data word is read from memory into the output shift register. one of the pins, qj, is connected to r and advances the read pointer every j-th serial output clock. fl / rt first load/ i this is a dual-purpose pin. in multiple-device mode, fl / rt is grounded to indicate the first retransmit device loaded. in single-device mode, fl / rt acts as the retransmit input. single-device mode is initiated by grounding the xi pin. xl expansion in i in single-device mode, xi is grounded.in depth expansion or daisy chain mode, xi is con nected to the xo pin of the previous device. oe output enable i when oe is low, both parallel and serial outputs are enabled. when oe is high, the parallel output buffers are placed in a high-impedance state. q 0 -q 8 data outputs / o in a parallel output configuration - data outputs for 9-bit wide data. in a serial output serial output configuration - one of nine output pins used to select the serial output word width. word width select ff full flag o ff is asserted low when the fifo is full and further write operations are inhibited. when the ff is high, the fifo is not full and data can be written into the fifo. ff-1 full-1 flag o ff-1 goes low when the fifo memory array is one word away from being full. it will remain low when every memory location is filled. 2753 tbl 04
5.37 4 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges pin description (continued) symbol name i/o description xo / hf expansion out/ o hf is low when the fifo is more than half-full in the single device or width expansion modes. the hf will remain low until the difference between the write and read pointers is less than or equal to one-half of the fifo memory. in depth expansion mode, a pulse is written from xo to xi of the next device when the last location in the fifo is filled. another pulse is sent from xo to xl of the next device when the last fifo location is read. aef almost-empty/ o when aef is low, the fifo is empty to 1/8 full or 7/8 full to completely full. if aef is high, then the fifo is greater than 1/8 full, but less than 7/8 full. ef+1 empty+1 flag o ef+ 1 is low when there is zero or one word word in the fifo memory array. ef empty flag o ef goes low when the fifo is empty and further read operations are inhibited. ff is high when the fifo is not empty and data reads are permitted. sl serial input i data input for serial data. so serial output o data output for serial data. sicp serial input clock i this pin is the serial input clock. on the rising edge of the sicp signal, new serial data bits are read into the serial input shift register. socp serial output i this pin is the serial output clock. on the rising edge of the socp signal, new serial data bits are read from the serial output shift register. six serial input i six controls the serial input expansion for word widths greater than 9 bits. in a serial input configuration, the six pin of the least significant device is tied high. the six pin of all other devices is connected to the d 8 pin of the previous device. in parallel input configurations or serial input configurations of 9 bits or less, six is tied high. sox serial output i sox controls the serial output expansion for word widths greater than 9 bits. in a serial output configuration, the sox pin of the least significant device is tied high. the sox pin of all other devices is connected to the q 8 pin of the previous device. in parallel output configurations or serial output configurations of 9 bits or less, sox is tied high. si /pi serial/parallel input i when this pin is high, the fifo is in a parallel input configuration and accepts input data through d 0 -d 8 . when si /pi is low, the fifo is in a serial input configuration and data is input through sl. so /po serial/parallel output i when this pin is high, the fifo is in a parallel output configuration and sends output data through q 0 -q 8 . when so /po is low the fifo is in a serial output configuration and data is input through so. gnd ground one ground pin for the dip package and five ground pins for the lcc/plcc packages. v cc power one + 5v power pin. 2753 tbl 05 half-full flag almost-full flag clock expansion expansion
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 5 ac test conditions input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 2753 tbl 07 1.1k w 30pf* 680 w 5v d.u.t. 2753 drw 04 figure 1. ouput load *including jig and scope capacitances or equivalent circuit dc electrical characteristics (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c) idt72103/72104 commercial t a = 35, 50ns symbol parameter min. typ. max. unit i il (1) input leakage current C1 1 m a (any input) i ol (2) output leakage current C10 10 m a v oh output logic "1" voltage, 2.4 v i out = -2ma (4) v ol output logic "0" voltage, 0.4 v i out = 8ma (5) i cc1 (3) average v cc power supply current 90 140 ma i cc2 (3) average standby current 8 12 ma ( r = w = rs = fl / rt = v ih ) (socp = sicp = v il ) i cc3 (l) (3,6) power down current 2 ma notes: 2753 tbl 06 1. measurements with 0.4 v in v cc . 2. r 3 v ih , socp vil, 0.4 v out v cc . 3. i cc measurements are made with outputs open. 4. for so, i out = -8ma. 5. for so, i out =16ma. 6. socp = sicp 0.2v; other inputs = v cc -0.2v.
5.37 6 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges ac electrical characteristics (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c) commercial idt72103l35 idt72103l50 idt72104l35 idt72104l50 timing symbol parameter min. max. min. max. unit figure f s parallel shift frequency 22.2 15 mhz f socp serial-out shift frequency 50 40 mhz f sicp serial-in shift frequency 50 40 mhz parallel-output mode timings t a access time 35 50 ns 4 t rr read recovery time 10 15 ns 4 t rpw read pulse width 35 50 ns 4 t rc read cycle time 45 65 ns 4 t wlz write pulse low to data bus at low-z (1) 5 15 ns 15 t rlz read pulse low to data bus at low-z (1) 510ns4 t rhz read pulse high to data bus at high-z (1) 20 30 ns 4 t dv data valid from read pulse high 5 5 ns 4 parallel-input mode timings t ds data set-up time 18 20 ns 3 t dh data hold time 0 0 ns 3 t wc write cycle time 45 50 ns 3 t wpw write pulse width 35 40 ns 3 t wr write recovery time 10 10 ns 3 reset timings t rsc reset cycle time 45 50 ns 2,18 t rs reset pulse width 35 40 ns 2,18 t rss reset set-up time 35 40 ns 2,18 t rsr reset recovery time 10 10 ns 2,17,18 reset to flag timings t rsf1 reset to ef , aef , and ef+1 low 45 65 ns 2 t rsf2 reset to hf , ff , and ff-1 low 45 65 ns 2 reset to output timings ?serial mode only t rsql reset going low to q 0-8 low 20 20 ns 18 t rsqh reset going high to q 0-8 high 20 20 ns 18 t rsdl reset going low to d 0-8 low 20 20 ns 17 retransmit timings t rtc retransmit cycle time 45 50 ns 5 t rt retransmit pulse width 35 40 ns 5 t rts retransmit set-up time 35 40 ns 5 t rtr retransmit recovery time 10 10 ns 5 t rtf retransmit to flags 35 50 ns 5 parallel mode flag timings t ref read low to ef low 30 45 ns 6 t rff read high to ff high 30 45 ns 7 t rf read high to transitioning hf , aef and ff-1 45 65 ns 8,9,10 t re read low to ef+1 low 45 65 ns 11 t rpe read pulse width after ef high 35 40 ns 15 t wef write high to ef high 30 45 ns 6 t wff write low to ff low 30 45 ns 7 t wf write low to transitioning hf , aef and ff-1 45 65 ns 8,9,10 t we write high to ef+1 high 45 65 ns 11 t wpf write pulse width after ff high 35 40 ns 16 2753 tbl 08 note: 1. values guaranteed by design, not tested.
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 7 ac electrical characteristics (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c) commercial idt72103l35 idt72103l50 idt72104l35 idt72104l50 timing symbol parameter min. max. min. max. unit figure depth expansion mode timings t xol read/write to xo low 35 50 ns 13 t xoh read/write to xo high 35 50 ns 13 t xi xi pulse width 35 50 ns 14 t xir xi recovery time 10 10 ns 14 t xis xi set-up time 15 15 ns 14 serial-input mode timings t s2 serial data in set-up time to sicp rising edge 12 15 ns 19 t h2 serial data in hold time to sicp rising edge 0 0 ns 19 t s3 six set-up time to sicp rising edge 5 5 ns 19 t s4 w set-up time to sicp rising edge 5 5 ns 19 t h4 w hold time to sicp rising edge 7 7 ns 19 t sicw serial in clock width high/low 8 10 ns 19 t s5 si/pi set-up time to sicp rising edge 35 50 ns 19 serial-output mode timings t s6 so/po set-up time to socp rising edge 35 50 ns 20 t s7 sox set-up time to socp rising edge 5 5 ns 20 t s8 r set-up time to socp rising edge 5 5 ns 20 t h8 r hold time to socp rising edge 7 7 ns 20 t socw serial out clock width high/low 8 10 ns 20 serial mode recovery timings t refso recovery time socp after ef goes high 35 80 ns 22 t rffsi recovery time sicp after ff goes high 15 15 ns 23 serial mode flag timings t socef socp rising edge (bit 0- last word) to ef low 20 25 ns 22 t socff socp rising edge (bit 0- first word) to ff high 30 40 ns 24 t socf socp rising edge to ff-1 , hf , aef high 30 40 ns 24,26 t socf socp rising edge to aef , ef , ef+1 low 30 40 ns 22,26 t sicef sicp rising edge (last bit-first word) to ef high 45 65 ns 21 t sicff sicp rising edge (bit 1-last word) to ff low 30 40 ns 23 t sicf sicp rising edge to ef+1 , aef high 45 65 ns 21,25 t sicf sicp rising edge to ff-1 , hf , aef high 45 65 ns 23,25 serial-input mode timings t pd1 sicp rising edge to d (1) 5 17 5 20 ns 17,19 serial-output mode timings t pd2 socp rising edge to q (1) 5 17 5 20 ns 20 t sohz socp rising edge to so at high-z (1) 5 16 5 16 ns 20 t solz socp rising edge to so at low-z (1) 5 22 5 22 ns 20 t sopd socp rising edge to valid data on so 18 18 ns 20 output enable/disable timings t oehz output enable to high-z (disable) (1) 16 16 ns 12 t oelz output enable to low-z (enable) (1) 55ns12 t aoe output enable to data valid (q 0-8 ) 20 22 ns 12 note: 2753 tbl 09 1. values guaranteed by design, not tested.
5.37 8 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges general signal description inputs: data inputs (d 0 -d 8 ) the parallel-in mode is selected by connecting the si /pi pin to v cc . d 0 -d 8 are the data input lines. the serial-input mode is selected by grounding the si /pi pin. the d 0 -d 8 lines are control output pins used to program the serial word width. reset ( rs ) reset is accomplished whenever the rs input is taken to a low state. both internal read and write pointers are set to the first location during reset. a reset is required after power up before a write operation can take place. both read ( r ) and write ( w ) inputs must be high during reset. write ( w ) a write cycle is initiated on the falling edge of w provided the full flag ( ff ) is not asserted. data set-up and hold times must be met with respect to the rising edge of w . data is stored in the ram array sequentially and independently of any on going read operation. when the fifo is full, the ff will go low inhibiting further write operations to prevent data overflow. after a valid read operation is completed, the ff will go high after t rff allowing a valid write to begin. read ( r ) a read cycle is initiated on the falling edge of r , provided the ef is not set. data is accessed on a first-in/first out basis independent of any on going write operations. after r goes high, the data outputs (q 0 -q 8 ) go to a high-impedance condition until the next read operation. when all the data has been read from the fifo, the ef will go low, and q 0 -q 8 will go to a high-impedance state inhibiting further read opera- tions. after the completion of a valid write operation, the ef will go high after t wef allowing a valid read to begin. first load/retransmit ( fl / rt ) in the depth-expansion mode, the fl / rt pin is grounded to indicate that it is the first device loaded. in the single-device mode, the fl / rt pin acts as the retransmit input. the single- device mode is initiated by grounding the expansion-ln ( xi ) pin. the idt72103/72104 can be made to retransmit data when the rt input is pulsed low. a retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. during retransmit, r and w must be set high and the ff will be affected depending on the relative locations of the read and write pointers. this feature is useful when less than 2048/4096 writes are performed between resets. the retransmit feature is not available in the depth expansion mode. expansion in ( xi ) the xi pin is grounded to indicate an operation in the the single-device mode. in the depth expansion or daisy-chain mode, the xi pin is connected to the xo pin of the previous device. output enable ( oe ) when oe is high, the parallel output buffers are tristated. when oe is low, both parallel and serial outputs are en- abled. serial input (si) serial data is read into the serial input register via the sl pin. in both depth and serial width expansion modes, the serial- input signals of the different flfos in the expansion array are connected together. serial input clock (sicp) serial data is read into the serial input register on the rising edge of the sicp signal. in both depth and serial width expansion modes, the sicp signals of the different flfos in the expansion array are connected together. serial output clock (socp) new serial data bits are read from the serial output register on the rising edge of the socp signal. in both depth and serial width expansion modes, the socp signals of the different flfos in the expansion array are connected together. serial input expansion (six) the slx pin is tied high for single-device serial or parallel input operation. in a serial input configuration, the six pin of the least significant device is tied high. the six pin of all other devices is connected to the d 8 pin of the previous device. serial output expansion (sox) the sox pin is tied high for single-device serial or parallel output operation. in a serial output configuration, the sox pin of the least significant device is tied high. the sox pin of all other devices is connected to the q 8 pin of the previous device. serial/parallel input ( si /pi) the si /pi pin programs whether the idt72103/72104 accepts parallel or serial data as input. when this pin is low, the fifo expects serial data and the d 0 -d 8 pins become output pins used to program the write signal and the serial input word width. for instance, connecting d 8 to w will program a serial word width of 9 bits; connecting d 7 to w will program a serial word width of 8 bits and so on. serial/parallel output ( so /po) the so /po pin programs whether the idt72103/72104 outputs parallel or serial data. when this pin is low, the fifo expects serial data and the q 0 -q 8 pins output signals used to program the read signal and the serial output word width.
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 9 almost?mpty or almost?ull flag ( aef ) the aef asserts low if there are 0-255 or 1793-2048 bytes in the idt72103, 2k x 9 fifo. the aef asserts low if there are 0-511 or 3585-4096 bytes in the idt72104, 4k x 9 fifo. empty?lus?ne flag ( ef+1 ) in the parallel-output mode, the ef+1 flag is asserted low when there is one word or less in the fifo. it will remain low when the fifo is empty. in the serial-output mode, the ef+1 flag operates as an ef+2 flag. it goes low when the second to the last word is read from the ram array and is ready to be shifted out. empty flag ( ef ) ?parallel?ut mode when the fifo is in the parallel out mode and there is only one word in the fifo, the falling edge of the r line will cause the ef line to be asserted low. this is shown in figure 6. the ef is then de-asserted high by either the rising edge of w or the rising edge of sicp, as shown in figure 6. empty flag ?serial?ut mode the use of the ef is important for proper serial-out opera- tion when the fifo is almost empty. the ef flag is asserted low after the first bit of the last word is shifted out. this is shown in figure 22. table 1 ?status flags number of words in fifo (1) idt72103 idt72104 ff ff-1 aef hf ef+1 ef 00hhlhll 1 1 hhlhlh 2-255 2-511 h h l h h h ' 256-1024 512-2048 h hhhhh 1025-1792 2049-3584 h h h l h h 1793-2046 3585-4094 h h l l h h 2047 4095 h l l l h h 2048 4096 l l l l h h note: 2753 tbl 10 1. ef+1 acts as ef+2 in the serial out mode. outputs: data outputs (q 0 ? 8 ) data outputs for 9-bit wide data. these output lines are in a high-impedance condition whenever r is in a high state. the serial output mode is selected by grounding the so /po pin. the q 0 -q 8 lines are control pins used to program the serial word width. serial output (so) serial data is output on the so pin. in both depth and serial width expansion modes the serial output signals of the different flfos in the expansion array are connected to- gether. following reset, so is tristated until the first rising edge of the serial out clock (socp) signal. data is clocked out least significant bit first. in the serial width expansion mode, so is tristated again after the ninth bit is output. full flag ( ff ) ff is asserted low when the fifo is full. when the fifo is full, the internal write pointer will not be incremented by any additional write pulses. full flag ?serial in mode when the fifo is loaded serially, the serial in clock (sicp) asserts the ff . on the second rising edge of the sicp for the last word in the fifo, the ff will assert low, and it will remain asserted until the next read operation. note that when the ff is asserted, the last sicp for that word will have to be stretched as shown in figure 23. full flag ?parallel?n mode when the fifo is in the parallel-ln mode, the falling edge of w asserts the ff (low). the ff is then de-asserted (high) by subsequent read operations - either serial or parallel. full?inus ?one flag ( ffC1 ) the ffC1 flag is asserted low when the fifo is one word away from being full. it will remain asserted when the fifo is full. expansion out/half?ull flag ( xo / hf ) in the single-device mode, the xo / hf pin operates as a hf pin when the xl pin is grounded. after half of the memory is filled, the hf will be set to low at the falling edge of the next write operation. it will remain set until the difference between the write pointer and read pointer is less than or equal to one- half of the fifo total memory. the hf is then reset by the rising edge of the read operation. in the multiple-device mode, the xi pin is connected to the xo pin of the previous device. the xo pin signals a pulse to the next device when the previous device reaches the best location of memory in the daisy chain configuration.
5.37 10 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges parallel timings: 2753 drw 07 r t rc q 0C8 t rpw t rr t rlz t dv t a t rhz valid data figure 4. read operation in parallel data out mode figure 2. reset 2753 drw 05 r w rs aef, ef+1, ef ff-1, hf, ff t rsc t rs t rss t rsr t rss t rsf1 t rsf2 figure 3. write operation in parallel data in mode 2753 drw 06 w t wc 0C8 t wpw t wr t ds t dh 2753 drw 08 w, r rt t rt t rtc t rtr t rts flag valid all flags t rtf figure 5. retransmit
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 11 r (1) ef w t ref (2) (3) t wef 2753 drw 09 notes: 1. data is valid on this edge. 2. the empty flag is asserted by r in the parallel-out mode and is specified by t ref . the ef flag is deasserted by the rising edge of w . 3. first rising edge of write after ef is set. figure 6. empty flag timings in parallel out mode r ff w t rff (1) t wff 2753 drw 10 note: 1. for the assertion time, t wff is used when data is written in the parallel mode. the ff is de-asserted by the rising edge of r . figure 7. full flag timings in parallel-in mode r aef w t wf 2753 drw 11 t rf almost empty almost empty r aef w t wf 2753 drw 12 t rf almost full figure 8. almost-empty flag region figure 9. almost-full flag region
5.37 12 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges r hf, ff-1 w t wf 2753 drw 13 t rf figure 10. half-full and full-minus-1 flag timings r ef+1 w t re 2753 drw 14 t we figure 11. empty+1 flag timings 2753 drw 15 oe r t rc t rr t oelz data 1 data 1 t dv terminate read cycle t aoe t oehz t a t rlz second read by controlling oe q 0-8 figure 12. output enable timings 2753 drw 16 w r xo write to last physical location t xol t xol t xoh read from last physical location t xoh figure 13. expansion-out
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 13 figure 14. expansion-in figure 15. read data flow-through mode figure 16. write data flow-through mode 2573 drw 17 w r xi write to first physical location t xis read from first physical location t xis t xi t xir 2753 drw 18 w d r t rpe n ef q n t wlz t wef t a t ref valid data out 2753 drw 19 r d w n ff q n t ds t dh t a t wff t rff t wpf data in valid data out valid
5.37 14 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges serial timings: 2753 drw 20 rs t rs t rss sicp 0 i-1 i 0i t rsr (1) (1) sicp t pd1 t rsdl d 0 d 1-8 t pd1 note: 1. sicp should be in the steady low or high during t rss . the first low-high (or high-low) transition can begin after t rsr . figure 17. reset timings for serial-in mode 2753 drw 21 rs t rs t rss socp t rsr (1) (1) socp t rsql q 0-8 t rsc t rsqh note: 1. socp should be in the steady low or high during t rss . the first low-high (or high-low) transition can begin after t rsr . igure 18. reset timings for serial-out mode
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 15 notes: 1. after so /po has been set up, it cannot be dynamically changed; it can only be changed after a reset operation. 2. for single device: read out the last bit after ef is asserted. for serial width expansion mode: read out the last bit of the current memory location from the active device. 3. for single device: the operation starts after reset. for serial width expansion mode: read the first bit of the current memory location from the active device. figure 20. read operation in serial-out mode 2753 drw 23 socp sox t socw 1/t socp 0 n C 1 t s7 1 t socw t s6 so/po t s8 t pd2 qi r t h8 (1) (2) so t sohz so (3) t solz t sopd 2753 drw 22 sicp six si t sicw 1/t sicp 0 1 n C 1 t s3 2 (1) t sicw t s5 t s2 t h2 si/pi t s4 (2) t pd1 di w t h4 (2) (3) notes: 1. for the stand alone mode, n 3 4 and the input bits are numbered 0 to n-1. 2. for the recommended interconnections, di is to be directly tied to w and the t s4 and t h4 requirements will be satisfied. for users that modify w externally, t s4 and t h4 requirements have to be met. 3. after si /pi has been set up, it cannot be dynamically changed; it can only be changed after a reset operation. figure 19. write operation in serial-ln mode
5.37 16 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges 2753 drw 24 sicp t sicef first serial-in word second serial-in word third serial-in word 0 1 n C 1 0 1 n C 1 t pd1 r ef 0 ef+1 d n-1 =w (2) t sicf t re (3) (1) t ref notes: 1. parallel read shown for reference only. can also use serial output mode. 2. the empty flag is de-asserted after the nC1 rising edge of sicp of the first serial-in word. in the serial-out mode, a new read operation can begin t refso after ef goes high. in the parallel-out mode, a new read operation can occur immedately after ff goes high. 3. the ef+1 flag is de-asserted after the nC1 rising edge of sicp of the second serial-in word. figure 21. empty flag and empty+1 flag de-assertion in the serial-ln mode 2753 drw 25 socp serial word b last serial word 01 t socf w ef+1 r=q n-1 t socef n-2 n-1 01 n-2 n-1 01 n-2 n-1 01 t refso (2) (3) t wef word a word b third word (1) ef serial word a notes: 1. parallel write shown for reference only. can also use serial input mode. 2. the empty flag ( ef ) is asserted in serial-out mode by using the t socef parameter. this parameter is measured in the worst case condition from the rising edge of the socp used to clock data bit 0. whenever ef goes low, there is only one word to be shifted out. in the parallel-ln mode, the ef flag is de-asserted by the rising edge of w. in the serial-ln mode, the ef flag is de-asserted by the rising edge of w . 3. first write rising edge after ef is set. 4. once ef has gone low and the last bit of the final word has been shifted out, socp should not be clocked until ef goes high. figure 22. empty flag and empty+1 flag assertion in the serial-out mode (fifo being emptied)
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 17 2753 drw 26 sicp next to last serial word last serial word 01 t sicf r ff-1 w=d n-1 t sicff n-2 n-1 01 n-2 n-1 01 t rffsi (1) (2) t rff ff 2753 drw 27 socp t socff first serial-out word second serial-out word 0 1 n C 1 0 1 n C 1 t pd2 w ff ff-1 q n+1 = r (2) t socf t wff t wf (1) notes: 1. the full flag is asserted in the serial-ln mode by using the t sicff parameter. this parameter is measured in the worst case condition from the rising edge of sicp following a (t pd1 +t wff ) delay from the first sicp rising edge of the last word. 2. first read rising edge after ff is set. 3. after ff goes low and the last bit of the final word has been clocked in, sicp should not be clocked until ff goes high. figure 23. full flag and full-1 flag assertlon in the serial-ln mode (fifo being filled) notes: 1. the fifo is full and a new read sequence is started. 2. on the first rising edge of socp, the ff is de-asserted. in the serial-ln mode, a new write operation can begin following t rffs1 after ff , goes high. in the parallel-ln mode, a new write operation can occur immediately after ff goes high. 3. the ff-1 flag is de-asserted after the first socp of the second serial word. figure 24. full flag and full-1 flag de-assertion in the serial-out mode
5.37 18 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges figure 26. half-full, almost-full and almost-empty timings for serial-out mode 2753 drw 29 socp 0 1 n C 1 w hf t socf t wf t socf 0 half-full +1 half-full (1/2) half-full (1/2) aef almost-full (7/8 full) almost-full + 1 (7/8 full+1) almost-full (7/8 full) aef almost-empty C 1 (1/8 fullC1) almost-empty (1/8 full) almost-empty C 1 (1/8 fullC1) t wf 2753 drw 28 sicp 0 1 n C 1 r hf t sicf t rf t sicf 0 half-full (1/2) half-full + 1 half-full + 1 aef almost-full + 1 (7/8 full + 1) t rf almost-full (7/8 full) almost-full + 1 (7/8 full + 1) aef almost-empty (1/8 full) almost-empty C 1 (1/8 fullC1) almost-empty (1/8 full) figure 25. half-full, almost-full and almost-empty timings for serial-in mode
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 19 enable and disable timings for oe are shown in figure 12. single device mode a single idt172103/72104 may be used when application requirements are for 2048/4096 words or less. the idt72103/ 72104 is in the single device configuration when the expan- sion in ( xl ) control input is grounded (see figure 27). in this mode, the hf/xo is used as a half-full flag. wldth expanslon mode word width may be increased simply by connecting the corresponding input control signals of multiple devices. sta- tus flags can be detected from any one of the connected devices. figure 28 demonstrates an 18-bit word width by using two idt72103/72104s. any word width can be attained by adding additional idt72103/72104. operating description parallel operating modes: parallel data input by setting si /pi high, data is written into the fifo in parallel through the d0-d8 input data lines. parallel data output by setting so /po high, the parallel-out mode is chosen. in the parallel-out mode, as shown in figure 4, data is available ta after the falling edge of r and the output bus q goes into high-impedance after r goes high. alternately, the user can access the fifo by keeping r low and enabling data on the bus by asserting oe . when r is low, the oe is high and the output bus is tri-stated. when r is high, the output bus is disabled irrespective of oe . the figure 27. block diagram of single 2048 x 9/4096 x 9 fifo in parallel mode 2573 drw 30 idt 72103/04 data write full flag full-minus-one (w) (d) (ff) (ff-1) 9 data read empty flag empty-plus-one (r) (q) (ef) (ef+1) 9 hf half-full flag expansion in (xi) out in almost full (aef) reset (rs) almost empty (aef) retransmit (rt) ouput enable (oe) (si/pi) (so/po) v cc v cc
5.37 20 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges input configuration table serial input width expansion parallel single least significant all other most significant pin input device device devices device si /pi high low low low low sl high or low input data input data input data input data sicp high or low input clock input clock input clock input clock six high high high d 8 of next least d 8 of next least significant device significant device w write control d i d i of most d i of most d i of most significant device significant device significant device d 0 -d 8 input data no connect no connect except d 8 no connect except d 8 no connect except d i except d i d i (1) w w of all devices d 8 six of next most six of next most significant device significant device note: 2753 tbl 11 1. d i refers to the rnost significant bit of the serial word. if multiple devices are width cascaded, d i is the rnost significant bit from the most significant device. output configuration table serial output width expansion parallel single least significant all other most significant pin output device device devices device so /po high low low low low so output data output data output data output data socp high or low output clock output clock output clock output clock sox high high high q 8 of next least q 8 of next least significant device significant device r read control q i q i of most q i of most q i of most significant device significant device significant device q 0 -q 8 output data no connect no connect except q 8 no connect except q 8 no connect except qi except d i q i (1) r r of all devices q 8 sox of next most sox of next most significant device significant device note: 2753 tb l 12 1. q i refers to the most significant bit of the serial word. if multiple devices are width cascaded, q i is the rnost significant bit from the most significant device.
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 21 note: 1. flag detection is accomplished by monitoring all the flag signals of either (any) device used in the width expansion configuration. do not connect any flag signals together. figure 28. block diagram of 2048 x 18/4096 x 18 fifo memory used in width expansion in parallel mode 2753 drw 31 idt 72103/04 data write full flag reset (w) (d) (ff) (rs) 9 read empty flag retransmit (r) (ef) (rt) hf (xi) 18 idt 72103/04 hf 9 (xi) 9 9 (q) data 18 out in (so/po) (si/pi) v cc (si/pi) (so/po) v cc output enable (oe) truth tables table 2: reset and retransmit single device configuration/width expansion in parallel mode inputs (2) internal status (1) outputs mode rs rs fl fl xi xi read pointer write pointer aef aef , ef ef ff ff hf hf reset 0 x 0 location zero location zero 0 1 1 retransmit 1 0 0 location zero unchanged x x x read/write 1 1 0 increment (1) increment (1) xxx notes: 2753 tbl 13 1. pointer will increment if appropriate flag is high. 2. rs = reset input, fl / rt = first load/retransmit, ef = empty flag output, ff = full flag output, xi = expansion input.
5.37 22 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges note: 1. si /pi and so /po pins are tied to vcc. figure 29. block diagram of 6,144 x 9/12,288 x 9-fifo memory, depth expansion in parallel mode 2753 drw 32 ef idt 72103/04 xo ff 9 9 fl vcc ef idt 72103/04 xo ff 9 fl xi q r ef idt 72103/04 xo ff 9 fl xi xi rs empty w 9 d full depth expansion (daisy chain) mode the idt72103/4 can be easily adapted to applications where the requirements are for greater than 2048/4096 words. figure 29 demonstrates depth expansion using three idt72103/4s. any memory depth can be attained by adding additional idt72103/4s. the idt72103/4 operates in the depth expansion configuration when the following conditions are met: 1. the first device must be designated by grounding the first load ( fl ) control input pin. 2. all other devices must have the fl pin in the high state. 3. the expansion out ( xo ) pin of each device must be tied to the expansion in ( xl ) pin of the next device. see figure 29. 4. external logic is needed to generate a composite full flag ( ff ) and empty flag ( ef ). this requires the or-ing of all efs and or-ing of all ffs (i.e., all must be set to generate the correct composite ff or ef ). see figure 29. 5. the retransmit ( rt ) function and half-full flag ( hf ) are not available in the depth expansion mode.
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 23 note: 1. si/pi and so/po pins are tied to vcc. figure 30. bidirectional fifo mode note: 1. si/pi and so/po pins are tied to vcc. 2. for depth expansion block see depth expansion section and figure 29. 3. for flag detection see width expansion section and figure 28. figure 31. compound fifo expansion compound expansion mode the two expansion techniques described above can be applied together in a straightforward manner to achieve large fifo arrays (see figure 31). 2573 drw 33 idt 72103/04 system b d b 0C8 w b ff b q a 0C8 ef a hf a r a idt 72103/04 w a ff a hf b ef b r b q b 0C8 d a 0C8 system a oe oe 2753 drw 34 idt72103/72104 depth expansion block qCq 08 dCd 08 qCq 08 idt72103/72104 depth expansion block qCq 917 dCd 917 qCq 917 idt72103/72104 depth expansion block dCd nC8 n dCd 0n dCd 9n dCd 18 n dCd nC8 n qCq nC8 n qCq nC8 n r, w, rs bidirectional mode applications requiring data buffering between two systems (each system capable of read and write operations) can be achieved by pairing idt72103/4 as shown in figure 30. both depth expansion and width expansion may be used in this mode.
5.37 24 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges serial operating modes: serial data input the serial input mode is selected by grounding the sl/pi line. the d0-8 lines are then outputs which are used to program the width of the serial word. they are taps off a digital delay line which are meant for connection to the w input. for instance, connecting d6 to w will program a serial word width of 7 bits, connecting d7 to w will program a serial word width of 8 bits and so on. by programming the serial word width, an economy of clock cycles is achieved. as an example, if the word width is 6 bits, then on every 6th clock cycle the serial data register is written in parallel into the fifo ram array. thus, the possible clock cycles for an extra 3 bits of width in the ram array are not required. the six signal is used for serial-ln expansion. when the serial word width is 9 or less, the six input must be tied high. when more than 9 bits of serial word width is required, more than one device is required. the six input of the least significant device must be tied high. the d8 pin of the least significant device must be tied to six of the next significant device. in other words, the six input of the most significant and intermediate devices must always be connected to the d8 of the next least significant device. figure 32 shows the relationship of the six, sicp and d0- 8 lines. in the stand alone case (figure 32), on the first low- to-hlgh of sicp, the d1-8 lines go low and the d0 line remains high. on the next sicp clock edge, the d1 goes high, then d2 and so on. this continues until the d line, which is connected to w , goes high. on the next clock cycle, after w is high, all of the d lines go low again and a new serial word input starts. in the cascaded case, the first low-to-hlgh sicp clock edge for a serial word will cause all timed outputs (d) to go low except for d0 of the least significant device. the d outputs of the least significant device will go high on consecu- tive clock cycles until d8. when d8 goes hlgh, the slx of the next device goes hlgh. on the next cycle after the six input is brought high, the d0 goes high; then on the next cycle d1 and so on. a di output from the most significant device is issued to create the w for all cascaded devices. the minimum serial word width is 4 bits and the maximum is virtually unlimited. when in the serial mode, the least significant bit of a serial stream is shifted in first. if the fifo output is in the parallel mode, the first serial bit will come out on q0. the second bit shifted in is on q1 and so on. in the serial cascade mode, the serial input (sl) pins must be connected together. each of the devices then receives serial information together and uses the six and d0-8 lines to determine whether to store it or not. the example shown in figure 34 shows the interconnec- tions for a serializing fifo that transfers data to the internal ram in 16-bit quantities (i.e. every 16 slcp cycles). this corresponds to incrementing the write pointer every 16 sicp cycles. once w goes high with the last serial bit in, sicp should not be clocked again until ff goes high. table 3: reset and first load truth table depth expansion/compound expansion mode inputs (2) internal status outputs mode rs rs fl fl xi xi read pointer write pointer ef ef ff ff reset-first 0 0 (1) location zero location zero 0 1 device retransmit all 0 1 (1) location zero location zero 0 1 other devices read/write 1 x (1) x x x x notes: 2753 tbl 14 1. xi is connected to xo of previous device. 2. rs = reset input, fl / rt = first load/retransmit, ef = empty flag ouput, ff = full flag output, xi = expansion input.
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 25 single device serial input configuration figure 32. serial-in mode where 8-bit parallel output data is read figure 33. serial-input circuitry delayed timing generator mux rgtr 9 w serial-input clock serial data in data in to fifo ram si/pi 9 data in/timed outputs d 0-8 2753 drw 35 sicp w v cc 0123456701234567 0 d 4 d 5 d 6 sicp six serial-in clock gnd q 0-7 wd 0 d 3 d 2 d 1 si serial-in data d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 8 v cc idt72103/4 si/pi so/po d 0 =1 d 7
5.37 26 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges note: 1. all si /pi pins are tied to gnd and so /po pins are tied to v cc . oe is tied low. for ff and ef connections see figure 29. figure 35. an 8k x 8 serial-in, parallel-out fifo figure 34. serial-in configuration for serial-in to parallel-out data of 16 bits serial input with depth expansion 2753 drw 38 sicp r q 0-7 d 7 si idt72104 six fl/rt xo sicp r q 0-7 w d 7 si idt72104 six fl/rt xi v cc q 0-7 r si sicp xi xo v cc v cc sox si/pi gnd v cc sox so/po v cc w si/pi gnd so/po v cc 2753 drw 37 sicp v cc 0 d of fifo #1 and six of fifo #2 8 sicp six serial-in clock gnd q 0-8 w d 8 si idt72103/104 fifo #1 17891014150 d of fifo #2 and w of fifo #1 and fifo #2 6 9 sicp six si serial-in data si/pi so/po v cc gnd si/pi so/po v cc q 0-6 w d 6 9 7 16-bit parallel output idt72103/104 fifo #2 serial input width expansion
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 27 serial input with width and depth expansion sicp r q 0-8 w d 8 si six v cc xi xo sicp r q 0-8 w d 8 si six v cc xi xo sicp r q 0-8 w d 8 si six xi xo sicp r q 0-8 w d 8 si six xi xo sicp r q 0-5 w d 5 si six xi xo sicp r q 0-5 w d 5 si six xi xo serial data in serial input clock p 0-8 p 9-17 p 18-23 read parallel data out 2753 drw 39 idt72104 idt72104 idt72104 idt72104 idt72104 idt72104 serial data output the serial output mode is selected by setting the so/po line low. when in the serial-out mode, one of the q1-8 lines should be used to control the r signal. in the serial-out mode, the q0-8 are taps off a digital delay line. by selecting one of these taps and connecting it to r, the width of the serial word to be read and shifted is programmed. for instance, if the q5 line is connected to the r input, on every sixth clock cycle a new word is read from the fifo ram array and begins to be shifted out. the serial word is shifted out least significant bit first. if the input mode of the fifo is parallel, the information that was written into the d0 bit will come out as the first bit of the serial word. the second bit of the serial stream will be the d1 bit and so on. in the stand alone case, the sox line is tied high and not used. on the first low-to-high of the socp clock, all of the q outputs except for q0 go low and a new serial word is started. on the next clock cycle, q1 will go high, q2 on the next clock cycle and so on, as shown in figure 37. this continues until the q line, which is connected to r, goes high at which point all of the q lines go low on the next clock and a new word is started. in the cascaded case, word width of more than 9 bits can note: 1. all si /pi pins are tied to gnd. so /po pins are tied to v cc . for fl / rt , ff and ef connections see figure 29. figure 36. an 8k x 24 serial-in, parallel-out fifo using six idt72104s be achieved by using more than one device. by tying the sox line of the least significant device high and the sox of the subsequent devices to q8 of the previous device, a cascaded serial word is achieved. on the first low-to-high clock edge of socp, all the q lines go low except for q0. just as in the stand alone case, on each consecutive clock cycle, each q line goes high in the order of least to most significant. when q8 (which is connected to the sox input of the next device) goes high, the d0 of that device goes high, thus cascading from one device to the next. the q line of the most significant device, which programs the serial word width, is connected to all r inputs. the serial data output (so) of each device in the serial word must be tied together. since the so pin is tri-stated, only the device which is currently shifting out is enabled and driving the 1-bit bus. figure 39 shows an example of the interconnections for a 16-bit serialized fifo. once r goes high with the last serial bit out, socp should not be clocked again until ef goes high.
5.37 28 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges 2753 drw 40 v cc socp sox serial-out clock gnd d 0-7 rq 0 so serial-out data q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 8 v cc idt72103/4 gnd parallel data in oe si/pi so/po socp r 0123456701234567 0 q 4 q 5 q 6 q 3 q 2 q 1 q 0 =1 q 7 note: 1. input data is loaded in 8-bit quantities and read out serially. figure 37. serial-out configuration
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 29 delayed timing generator mux serial-out register 9 r socp-serial output clock parallel-out data/ timed output q serial- output data (so) 0-8 so/po control circuit so/po output from ram array 2753 drw 41 9 figure 38. serial-output circuitry 2753 drw 42 socp v cc 0 q of fifo #1 and sox of fifo #2 8 socp sox serial-output clock gnd r q 8 so fifo #1 17891014150 q of fifo #2 and r of fifo #1 and fifo #2 6 socp sox so si/pi so/po v cc gnd si/pi so/po v cc d 0-8 r q 6 9 7 fifo #2 serial-out data d 0-6 parallel data in 16-bits wide note: 1. the parallel data in is tied to d0-8 of fifo #1 and d0-6 of fifo #2. figure 39. serial-output for 16-bit parallel data in
5.37 30 idt72103, idt72104 cmos parallel-serial fifo 2048 x 9, 4096 x 9 commercial temperature ranges serial output with depth expansion note: 1. all rs pins are connected together. all oe pins are connected low. all si /pi and so /po pins are grounded. figure 41. 128k x 1 serial-in serial-out fifo note: 1. all si /pi pins are tied to vcc and so /po pins are tied to gnd. oe is tied low. for ff and ef connections see figure 17. figure 40. an 8k x 8 parallel-in serial-out fifo serial in and serial out with width and depth expansion 2753 drw 43 socp r d 0-7 q 7 so idt72104 fl/rt xo socp r d 0-7 w q 7 so idt72104 fl/rt xi d 0-7 w so socp xi xo v cc v cc sox v cc sox w r w d 8 si six xi xo idt72104 sicp fl/rt ff ef q 8 so sox socp r w d 8 si six xi xo idt72104 sicp fl/rt ff ef q 8 so sox socp v cc v cc v cc v cc r w d 6 si six xi xo idt72104 sicp fl/rt q 6 so sox socp r w d 6 si six idt72104 sicp fl/rt q 6 so sox socp xi xo full flag empty flag socp so si sicp cc v 2753 drw 44 cc v
idt72103, idt72104 cmos parallel-serial fifo 2048 x 9 and 4096 x 9 commercial temperature ranges 5.37 31 ordering information commercial (0 c to +70 c) 40-pin plastic leaded chip carrier commerical commercial low power 2048 x 9-bit configurable parallel-serial fifo 4096 x 9-bit configurable parallel-serial fifo idt 2753 drw 45 x power xxx speed x package x process/ temperature range blank j 35 50 l xxxxx device type 72103 72104 (50mhz serial shift rate) (40mhz serial shift rate)

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